Summary
Overview
Work History
Education
Skills
Timeline
Interests
Awards
Generic

Bryan Hsieh

Embedded Engineer
London

Summary

A soon to graduate PhD candidate, presently working as a part time research assistant at a top university. Highly skilled and adept at tackling difficult engineering tasks. Experienced as demonstrated by the multitude of projects previously undertaken and a eager learner. Currently, looking for an opportunity to apply the skills and knowledge acquired in industry.

Overview

5
5
years of professional experience
17
17
years of post-secondary education
2
2
Languages

Work History

PhD/Research Assistant

Imperial College
London
10.2017 - Current


EEG Datalogger:

• Developed a miniature ( < 20mm by 17mm ), low power ( < 3mW ) neural logger to research sleep circuits in neuroscience.

• Proposed and implemented a highly accurate, unsupervised online/offline sleep stage scoring algorithm based on Gaussian Mixture Model and z-score normalization.
• Designed a custom multi activity Android BLE application for real time data verification and device control.
• Designed a custom GUI application based on the MVC framework using Qt creator for data acquisition and device configuration.
• Produced a BLE firmware for an ARM based SoC and highly optimized it for power and speed via the usage of DMA, data buffers and hardware interrupts.

• Designed a custom optogenetic coupler for optical fibers for closed loop stimulation in SolidWorks


Dementia Research:

• Wrote an automatic script to analyse, sleep score and collate large datasets of EEG and photometry recordings in MATLAB for Dementia research.


Rodent Tracking :

• Designed a system to automatically deliver video stimuli upon detection of movements using Raspberry Pie, OpenCV2 and Python.


UROP Internship

Altera
London
07.2015 - 09.2015

• Implemented a DNA alignment algorithm based on Burrows-Wheeler

transform for matching DNA reads to a known genome on multiple platforms.

• Investigated OpenCL as an alternative to HDL for programming FPGA's using Altera's OpennCL SDK and Stratix V board

• Compared the performance of the algorithm across different platforms and also against other existing algorithms such as Soap2 and Bowtie.

Education

Ph.D. - Electronic Microdevices For Neuroscience Research

Imperial College London
London, GB
10.2017 - Current

Master of Research - Neurotechnology

Imperial College London
London, GB
11.2016 - 11.2017

Master of Engineering - Biomedical Engineering

Imperial College London
London, GB
10.2012 - 10.2016

A Levels -

Wilmslow High School
Cheshire
07.2005 - 07.2012

Skills

  • C/C
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Timeline

PhD/Research Assistant

Imperial College
10.2017 - Current

Ph.D. - Electronic Microdevices For Neuroscience Research

Imperial College London
10.2017 - Current

Master of Research - Neurotechnology

Imperial College London
11.2016 - 11.2017

UROP Internship

Altera
07.2015 - 09.2015

Master of Engineering - Biomedical Engineering

Imperial College London
10.2012 - 10.2016

A Levels -

Wilmslow High School
07.2005 - 07.2012

Interests

  • Racket Sports ( Badminton, Squash & Tennis )
  • Travelling ( Culture & Food )
  • Cooking

Awards

Dean's List - 2013

IET Ambition Awards - 2012

Bryan HsiehEmbedded Engineer