SNEHA KESHAGANI
Newcastle,newcastle
Summary
Experienced Analog Layout Engineer with 7 years in the semiconductor industry, specializing in Analog/Mixed Signal Layout Design. Proficient in floorplanning, device matching, and verification (DRC, LVS, ERC). Skilled in working with advanced process nodes (TSMC 5nm/6nm/16nm/28nm/45nm/150nm) and collaborating with cross-functional teams to deliver high-quality, optimized circuit designs.
Overview
7
7
years of professional experience
Work History
Senior Layout Engineer
Cyient Limited
Hyderabad, india
04.2022 - 01.2025
- Led top-level Analog/Mixed Signal layout designs for high-speed and power management circuits.
- Ensured DRC, LVS, and ERC compliance.
- Collaborated with circuit designers to optimize floorplanning and matching techniques.
- Worked on advanced node technologies (TSMC 5nm, 6nm, 16nm) ensuring high-performance design delivery.
Senior Layout Engineer
Sankalp Semiconductor (HCL) Private Limited
Bangalore, india
01.2021 - 03.2022
- Designed and optimized complex analog blocks, ensuring area-efficient layouts.
- Managed multiple projects, balancing design constraints and process limitations.
- Worked extensively on power management and SerDes circuits, ensuring optimal signal integrity.
- Verified and resolved DRC, LVS, and antenna issues, reducing verification turnaround time.
Layout Design Engineer
RiseTime Semiconductors
Hyderabad, india
02.2018 - 01.2021
- Assisted in creating layout designs for sub-blocks in high-performance mixed-signal circuits.
- Supported efforts to reduce parasitic effects through improved routing and shielding techniques.
- Helped ensure compliance with design constraints while keeping signal paths short.
Education
Bachelor of Technology - Electronics and Communication Engineering
JNTUH
Hyderabad2017
Skills
- Mixed signal layout design
- Routing and floorplanning optimization
- Design rule checks
- FinFET and BCD technologies
- Cadence Virtuoso expertise
- Calibre verification tools
Projects
KEY PROJECTS
✅ **RX_BIAS (TSMC 5nm)** – Designed layout for sub-blocks Ensured DRC/LVS compliance and optimized matching constraints.
✅ **TX_BIAS (TSMC 5nm)** – Floor-planned and implemented signal flow-optimized layout with minimal abutment issues.
✅ **DVREG (TSMC 16nm)** – Developed a compact, high-efficiency power regulation layout with short routing paths.
✅ **Lock Detector Logic (TSMC 16nm)** – Designed and verified lock detection circuits, ensuring high accuracy in timing circuits.
✅ **PMIC Projects (TSMC 28nm, 40nm,55nm,65nm, 150nm)** – Developed layout for power management ICs, including Vreg, muxes, and clock circuits. Focused on efficient area utilization and signal integrity.
Timeline
Senior Layout Engineer
Cyient Limited
04.2022 - 01.2025
Senior Layout Engineer
Sankalp Semiconductor (HCL) Private Limited
01.2021 - 03.2022
Layout Design Engineer
RiseTime Semiconductors
02.2018 - 01.2021
Bachelor of Technology - Electronics and Communication Engineering
JNTUH