Prashanth Ravulapelli

Analog layout design engineer with 4 years of experience in the semiconductor industry, specializing in layout design and SSD validation at Micron Technology. Expertise includes fuse array layout implementation, bandgap reference, LDO layout design, and CMOS logic gate layout, with proficiency in DRC/LVS verification and physical verification methodologies using Cadence Virtuoso Layout XL. Strong foundation in semiconductor physics, CMOS manufacturing processes, and low-power circuit design, alongside knowledge of LDE, DFM, EMIR, and tape-out requirements. Skilled in Python and Linux, with a proven track record of cross-functional collaboration to produce high-quality, manufacturable semiconductor designs.

Takshila Institute of VLSI Technologies

• Completed industry-focused training in analog and mixed-signal layout design using Cadence Virtuoso Layout XL.
• Designed layouts for CMOS logic gates including Inverter, NAND, NOR, XOR, and other digital building blocks.
• Implemented Bandgap Reference layouts using matching techniques, common centroid placement, shielding, isolation, dummy devices, and parasitic-aware methodologies.
• Developed Low-Dropout Regulator (LDO) layouts considering routing optimisation, matching requirements, power integrity, and layout-dependent effects.
• Performed DRC and LVS verification to ensure layout correctness and manufacturability.

• Cadence Virtuoso Layout XL, Cadence Spectre
• Analog & Mixed-Signal Layout
• DRC, LVS, Physical Verification
• Fuse Array, LDO, Bandgap Reference Layout
• CMOS Layout Techniques
• Python, Linux, Git
• FPGA Design, VHDL, SystemVerilog
• PCIe Gen4/Gen5, NVMe

• Analog Layout Design Certification – Takshila Institute of VLSI Technologies
• PCB Design & Fabrication Certification

Low-Power LDO Regulator with Adaptive Biasing and Protection

• Designed a PMOS-based low-dropout regulator using Cadence Virtuoso and Cadence Spectre.
• Performed DC, AC, transient, and corner simulations to evaluate performance, stability, and reliability.
• Implemented adaptive biasing and protection techniques to improve efficiency and robustness.,

FPGA-Based 32-bit RISC-V Processor with UART

• Implemented a 32-bit RISC-V processor using VHDL and integrated UART communication functionality.
• Completed simulation, synthesis, implementation, and hardware validation using Xilinx Vivado.,

AMBA APB Protocol Verification using SystemVerilog & SVA

• Developed an APB slave design and verification environment using SystemVerilog.
• Created directed test scenarios and analysed simulation results using waveform debugging techniques.

Awarded Top-Tier Performance Rating at Micron Technology for engineering excellence and product qualification contributions.