Sharanya Selvam

Applications Engineer with 3 years of hands-on experience in FPGA prototyping workflows and EDA tool validation at Synopsys, a leading electronic design automation company. Currently pursuing Master's in Microelectronics Systems Design at University of Southampton. Experienced in working with multi-FPGA prototyping flows, supporting customer designs, and validating tool functionality across different applications. Proficient in ProtoCompiler (HAPS) platforms, TCL scripting, and Verilog HDL and System Verilog development.

Won second place in English Olympiad Examination.

Light Sensor using Linear integrated Circuits and LDR : A Light Detector or a Light Sensor is a device or circuit that detects the  intensity of the light incident on it. Different types of light detectors  are LDRs (or Light Dependent Resistors), Photo Diodes, Photo  Transistors, etc.  When the light falls on the LDR, the light stays off and when the light  stops falling on LDR, the LED glows. The circuit is designed using an  OP – AMP (Operational Amplifier-IC741)

AHB2APB bridge RTL design using Verilog HDL  

HDL: Verilog  EDA Tool: ISE-Xilinx  

The AHB to APB bridge is designed as an AHB slave which converts  AHB transactions to APB transactions by implementing pipelining at  the AHB slave interface. Thus, the bridge supports AHB burst transfers.  Architected the block level structure for the bridge.  Developed Verilog RTL for each block.  Verified each block with different transfers like single READ, WRITE &  Burst READ, WRITE.  Synthesized the design.

URBAN STREET VILLE BASED ON IoT:  A Framework, predominantly composed of Information and  Communication Technologies (ICT), to develop, deploy, and promote  sustainable development practices to address growing urbanization  challenges.  Used Arduino Mega (ATmega2560) Microcontroller Board, Sensors,  LEDS, Node Microcontroller Unit.  Software : Embedded C and Arduino IDE (in terms of Simulation).

SYNOPSYS, Bengaluru  

Worked as a contractor at Synopsys, Bengaluru through Ascent Staffing  Solutions. Exposed to FPGA EDA tools like Synplify Premier and HAPS  ProtoCompiler. Worked on setting up more than 40 Opencore Designs for  Prototyping flow validation. Also worked on Tri-states inference testing in  the Prototyping flow.  

MAVEN SILICON, Bengaluru  

VLSI Design Internship. Acquired knowledge of Verilog HDL and tools like  Xilinx ISE and Quartus Prime. Worked on a project named AHB2APB  bridge design.

ENTUPLE TECHNOLOGIES

Design and Verification using Verilog

SoC Design and Verification Workshop (MAVEN SILICON)

Digital System Design using Verilog HDL (GAT)

Overview of Digital Design with Verilog HDL, Hierarchical Modelling Concepts, Basic Concepts, Modules and Ports, Gate-Level Modelling, Dataflow Modelling, Behavioral Modelling.