Rudrapratap Roy

Proven Verification Engineer with expertise in ARM CPU core-level verification and RISC V processor design at ARM Embedded Technologies and Cadence Design Systems, respectively. Skilled in Verilog and System Verilog, demonstrating strong analytical abilities and a knack for enhancing testbench performance. Excelled in applying digital electronics knowledge to achieve significant project milestones.

RTL design and verification training

Maven Silicon|March 2021 – December 2021

Through this training, knowledge about FPGA design methodologies, FPGA architecture, advanced Verilog for verification, and System Verilog has been gained

• Capacitorless 1-T DRAM using 20 nm FinFET technology, Silvaco. A 20 nm junctionless FinFET was simulated using the Silvaco TCAD tool, and it was optimized to be used as a capacitorless DRAM by creating an extra storage region in the device, and by hole trapping
• Negative capacitance using FinFET 60 nm technology, Silvaco. A 60 nm FinFET was simulated using the Silvaco TCAD tool, and it was optimized to be used as a negative capacitance device by applying a ferroelectric region above the gate of the device
• Router 1x3 - RTL design and verification, Verilog, ModelSim, Quartus Prime. We designed a router that accepts data packets on a single 8-bit port and routes them to one of the three output channels: channel 0, channel 1, and channel 2
• The design of a subset of the 32-bit MIPS instruction set architecture,Verilog, ModelSim, Quartus Prime, and the ISA are the higher levels of abstraction that lie above the microarchitecture, and they are a set of instructions supported by the processor, which is the programming model of a processor with 32 general-purpose registers; the ALU block was designed and verified.
• Implementation of the FIFO, Verilog, ModelSim, Quartus Prime, and a synchronous FIFO was done using the first-in, first-out algorithm
• The design of the RISC Instruction Set Architecture, Verilog, and ModelSim was completed We designed each submodule of RISC, such as the control unit, ALU block, register block, etc., using Verilog, and verified it using a task-based testbench

• Gate qualified in 2019 with a score of 607
• Participated in division level under 17 chess competition
• Played under 17 football tournament
• Won prizes in the painting competition

• Playing guitar
• Painting
• Chess
• Football

• English
• Hindi

I solemnly declare that all the information furnished in this resume is true and correct to the best of my knowledge and belief., 

12/02/25, Bangalore, Karnataka

royrudrapratap@gmail.com, https://www.linkedin.com/in/rudrapratap-roy-b26b361b2/, 8917385215, 8093214557