Vidya Ramanarayanan

• Verification of System IPs like Generic Interrupt controller, System MMU, Embedded Logic Analyzer, Interconnect etc. on ARM based systems, on both simulation (Questa) and Emulation (Zebu, Strato, Z1) platforms
• Responsibilities span from feature investigation, test plan creation and review, writing stress test cases to create system level scenarios, verification sign-off for each milestone in accordance with the verification requirements
• Creation and integration of hardware & software irritators (Verilog, C) to induce more stress.
• Verification strategy formulation and implementation for AE IPs

• Worked on Emulation and Post Silicon validation of data center networking switches
• Worked on CPU subsystem subsystem validation, Fibre channel testing and validation, software quality assurance of Broadcom SW APIs
• Involved in the design, review of engineering boards for bring up of Baseband Modem chips (3G, LTE)
• Worked on the simulation and testing of various debug interfaces like JTAG, ETM, UART etc. Also, developed test RTL for USB, PCie, DigRF etc. Involved in the bring up of Baseband chip engineering boards

FPGA based board design including component selection, circuit design, schematic capture and review, layout guidance and assistance during board bringup and testing. Worked on DAQ system design, High Speed ADC based projects and board design for RF signal conditioning.