Summary
Overview
Work History
Education
Skills
Working Skills
Accumulated Skills
Websites
Technology Nodes
Timeline
Generic
Ahmed Karem

Ahmed Karem

Senior Physical Design Engineer
Cambridge

Summary

Enthusiastic Physical design engineer and a problem solver by heart with 6 and a half years of experience in Physical design, eager to contribute to team success through hard work, attention to detail. Clear understanding of Physical design & Implementation, Physical Verification, Timing Closure, and good knowledge in Fabrication & Lithography. Motivated to learn, grow, and excel in Physical Design & Implementation.

Overview

7
7
years of professional experience
5
5
years of post-secondary education

Work History

Senior Physical Implementation Engineer

Arm Ltd
05.2024 - Current

- Solutions Engineering group.
- GPU CSS and CSS
- Constraints development - Solutions Engineering group. - GPU CSS - CSS - Constraints development

Skills: SDC generation · Logic Synthesis · Floorplanning · Unified Power Format (UPF) · Timing Closure · Constraints development

Senior Physical Implementation Engineer

Arm Ltd
09.2023 - 05.2024

Senior role

Physical Implementation Engineer

Arm Ltd
05.2021 - 09.2023
  • Working on Methodology, RTL proving/feedback and Implementation for Arm Mali GPU
  • Responsibilities included, but not limited to:
  • Working with FE teams to understand the design architecture to drive optimal floorplanning and physical implementation through early RTL feedback
  • Driving Physical Design builds and optimization recipes for performance, power, and Area (PPA)
  • Managing and resolving design and flow issues related to PD, identifying potential solutions, and driving execution
  • Collaborating with methodology team to add features, flow enhancement, streamline Physical Design work, driving execution, and tracking progress
  • Running signoff analyses such as static timing and IR/EM analysis

Physical Design Engineer

ICpedia - Synopsys Inc.
06.2018 - 05.2021
  • Working on implementation of different Synopsys standard SERDES IPs across diff teams (Bluetooth Low Energy, MIPI Transceivers) that required the following:
  • Working with the design and architecture teams to construct the most efficient floorplans
  • Working with the design teams to help improve the RTL for implementation
  • Working on the Entire Back-end flow from performing synthesis, place and route and PPA optimizations
  • Running signoff analyses such as STA and timing closure, physical verification (LVS, DRC), IR drop/EM analysis
  • Working on flow enhancements along with other team members to fix issues and develop new methodologies

Education

Post-graduation Diploma - Digital Integrated Circuits

Information Technology Institute (ITI)
09.2017 - 06.2018

B.Sc. - Electronics and Communications

Faculty of Engineering - Fayoum University
Fayoum, Egypt
09.2013 - 06.2017

Skills

  • ASIC implementation

  • Synthesis Floorplanning

  • CTS, Power distribution

  • Place and Route

  • Under/Super Drive voltage corners

  • physical verification flows (LVS, DRC, ERC, ANT)

  • Manufacturability Analysis Scoring

  • Verilog, VHDL, SV

  • Logic Synthesis

  • RTL feedback

  • Physical Design

  • Low-power Design

  • Ultra-low power design

  • STA & Timing Closure

  • Physical Verification

  • Scripting (Python, TCL, Perl, Bash)

  • Digital Custom Design

  • Cadence

  • Synopsys

  • Ansys Redhawk

Working Skills

  • Ability to learn new tasks quickly.
  • Attention to detail and tenacity to chase down problems.
  • High Sense of Ownership.
  • Self-motivated.

Accumulated Skills

  • Experience with aspects of ASIC implementation including Synthesis, DFT insertion, Floorplanning, CTS, Power distribution, Place and Route and all aspects of timing, electrical and physical signoff.
  • Experience with multi-voltage, power gating and power retention technologies.
  • Experience with challenges for Under Drive and Super Under Drive (SUD) voltage corners.
  • Practical knowledge with hierarchical design approach, budgeting, and timing.
  • Experience with physical verification flows (LVS, DRC, ERC, ANT) and Fab process-related checks like Manufacturability Analysis Scoring (MAS).
  • Experience with managing and resolving design and flow issues related to physical design.

Technology Nodes

  • TSMC: 3FF, 5FF, 6/7ffc, 12ffc, 16ffc, 22ulp, 40ulp, 40ulpfs
  • GF: 12lp, 22fdsoi
  • UMC: 22ulp

Timeline

Senior Physical Implementation Engineer

Arm Ltd
05.2024 - Current

Senior Physical Implementation Engineer

Arm Ltd
09.2023 - 05.2024

Physical Implementation Engineer

Arm Ltd
05.2021 - 09.2023

Physical Design Engineer

ICpedia - Synopsys Inc.
06.2018 - 05.2021

Post-graduation Diploma - Digital Integrated Circuits

Information Technology Institute (ITI)
09.2017 - 06.2018

B.Sc. - Electronics and Communications

Faculty of Engineering - Fayoum University
09.2013 - 06.2017
Ahmed KaremSenior Physical Design Engineer