B. PUSHPALATHA
Watford,United Kingdom
Summary
Accomplished professional with extensive expertise in ASIC/SoC physical design, specialising in timing closure and ECO implementation. Demonstrates proficiency in physical verification, power and IR drop analysis, and automation scripting. Adept at managing signoff and tapeout processes with a strong foundation in cross-team collaboration and foundry experience. Skilled in process nodes expertise, design flows, data formats, and debugging. Proficient in using physical design tools and verification signoff tools to ensure seamless project execution. Committed to leveraging analytical thinking and problem-solving skills to drive innovation and efficiency within cross-functional teams.
Overview
6
6
years of professional experience
1
1
Certification
Work history
Physical Design & Verification Engineer
Current Company Name
2020.01 - 2026.02
- Executed full-chip physical design and verification flow for high-speed SoCs at 7nm/5nm/3nm process nodes, targeting mobile and AI accelerators.
- Defined and implemented floorplans with optimized power grid, placement blockages, and macro channeling for performance and routability.
- Conducted CTS, global/local routing, and post-route optimizations ensuring PPA (Power, Performance, Area) goals.
- Performed STA using PrimeTime, fixing setup/hold violations through ECOs.
- Executed DRC/LVS/DFM closure using Mentor Calibre and collaborated with foundry for clean signoff.
- Automated design tasks using Python/TCL, improving runtime efficiency by 25–30%.
- Coordinated with RTL, DFT, and Verification teams for design closure and silicon bring-up readiness.
- Key Achievements:
- Achieved first-pass silicon success for a 5nm SoC block integrated into Intel-compatible test platform.
- Reduced congestion hotspots by 35% through targeted placement and routing optimization.
- Developed reusable P&R; automation script later adopted across the design team.
- ECO implementations to fix setup and hold timing violations
- As an execution owner handled multiple GPU IP design blocks/sections/super-sections for full chip Layout Convergence
- Collaborated with multiple teams: [physical design ,clock , RV team] reporting root cause to fix the violations at early stage.
- Implemented Shift-Left Perspective for Faster Layout Convergence
- Handled base design and implementation
- Completed base tape-ins and metal tape-ins with gallery marking for various projects with all sign-off checks in physical verification process.
- Automated PV flows to reduce manual effort and time
Physical Design & Verification Engineer
INTEL TECHNOLOGY PRIVATE Ltd
Bangalore
2022.06 - 2025.05
- Executed full-chip physical design and verification flow for high-speed SoCs at 7nm/5nm/3nm process nodes, targeting mobile and AI accelerators.
- Defined and implemented floorplans with optimized power grid, placement blockages, and macro channeling for performance and routability.
- Conducted CTS, global/local routing, and post-route optimizations ensuring PPA (Power, Performance, Area) goals.
- Performed STA using PrimeTime, fixing setup/hold violations through ECOs.
- Executed DRC/LVS/DFM closure using Mentor Calibre and collaborated with foundry for clean signoff.
- Automated design tasks using Python/TCL, improving runtime efficiency by 25–30%.
- Coordinated with RTL, DFT, and Verification teams for design closure and silicon bring-up readiness.
- Key Achievements:
- Achieved first-pass silicon success for a 5nm SoC block integrated into Intel-compatible test platform.
- Reduced congestion hotspots by 35% through targeted placement and routing optimization.
- Developed reusable P&R; automation script later adopted across the design team.
Physical Design Engineer
UST GLOBAL [SEVITECH SYSTEMS PVT LTD]
2019.09 - 2022.04
- Executed block-level P&R; flow including synthesis handoff, placement, and CTS for 16nm SoC modules.
- Worked on timing closure and design convergence, achieving clean timing across PVT corners.
- Supported physical verification and power signoff activities with foundry partners.
- Performed EM/IR analysis, optimized routing for improved reliability, and assisted in chip-level integration.
- Delivered DRC/LVS-clean layouts 2 weeks ahead of schedule through improved signoff automation.
- Enhanced block-level PPA by 8% using congestion-driven placement refinements.
- Using ICC the tasks handled were Floor planning, Power Planning, Placement, CTS, Routing and STA.
- Responsible for rectilinear floor planning with minimum core utilization.
- Achieved optimum IR drop through exploratory changes in Floor planning and Power planning
- Performed various placement runs to reduce congestion and to meet the timing.
- Analyzed timing reports after placement stage, understanding the reasons behind setup and hold violations to fix the violations for good QOR report.
- Manual routing by detouring nets to clear DRC, LVS & ANT.
- Worked with physical verification team using scripting languages perl and tcl
- Automated high count of DRC/LVS violations to reduce
- Fixed critical DRC and LVS violations manually for live projects.
- ECO implementations to fix setup and hold timing violations
Education
Master of Technology - VLSI & Embedded Systems
K.S.School of Engineering and Management (VTU)
Bangalore, IndiaBachelor of Engineering - Electrical and Electronics Engineering
Acharya Institute of Technology (VTU)
Bangalore, IndiaSkills
- ASIC/SoC physical design
- Timing closure and ECO implementation
- Physical verification and analysis
- Power and IR drop analysis
- Automation scripting
- Signoff and tapeout processes
- Cross-team collaboration
- Foundry experience
- Process nodes expertise
- Design flows and methodologies
- Data formats proficiency
- Tapeout documentation and handling
- Debugging and root cause analysis
- Physical design tools proficiency
- Verification and signoff tools expertise
- Analytical thinking and problem solving
- Cross-functional collaboration skills
- Communication and documentation skills
Certification
- PG Diploma in Advanced Diploma in ASIC Design.
- RV-VLSI Design Center, Bangalore, India
- Synopsys IC Compiler II (ICC2) Advanced Physical Design
- VLSI Physical Design & Verification
PROJECT HIGHLIGHTS
5nm AI Accelerator SoC (High-Performance Core): Implemented hierarchical floorplanning and block integration; achieved 2.1 GHz frequency and zero signoff violations at tapeout., 16nm Low-Power IoT Design: Multi-voltage power planning and isolation strategy; reduced leakage by 12% through optimized power gating and retention cells.
Timeline
Physical Design & Verification Engineer
INTEL TECHNOLOGY PRIVATE Ltd
2022.06 - 2025.05
Physical Design & Verification Engineer
Current Company Name
2020.01 - 2026.02
Physical Design Engineer
UST GLOBAL [SEVITECH SYSTEMS PVT LTD]
2019.09 - 2022.04
Bachelor of Engineering - Electrical and Electronics Engineering
Acharya Institute of Technology (VTU)
Master of Technology - VLSI & Embedded Systems
K.S.School of Engineering and Management (VTU)