Yue Lu
Bishop's Stortford,Hertfordshire
Summary
Innovative ASIC Engineer with 7+ years of experience in high-performance and low power digital systems and micro-architecture definition. Expert in full-cycle RTL development (SystemVerilog) and High-Level Synthesis (HLS) for complex IP blocks. Proven track record in optimizing power, performance, and area (PPA) for production-level silicon. Passionate about advancing AI/ML hardware acceleration through cross-disciplinary collaboration and architectural exploration.
Overview
7
7
years of professional experience
9
9
years of post-secondary education
1
1
Certification
Work history
Staff SoC Design Engineer
ARM
Cambridge, Cambridgeshire
2025.02 - Current
- Take ownership of clock, power, and reset subsystems for ARM’s first Automotive CSS platform; integrated the GIC block and supported architecture maintenance, including ongoing interrupt map definition and updates.
- Designed and implemented an AXI-to-AXI-Stream bridge (AXI2A4S) with dynamic AXI ID remapping, enabling seamless conversion from >16-bit IDs to a 16-bit ID space.
Staff Design Engineer
Qualcomm
Cambridge
2019.02 - 2024.12
- Take design ownership of many key IP blocks in the following successful Bluetooth audio chips: QCC5100, QCC5171, Qualcomm S7 and S7 Pro. Collaborated with system, validation and implementation teams to meet all functional requirements, performance, power and area goals
- Designed and integrated Audio codec Receiver block using Cadence Stratus HLS (High-level-Synthesise), familiar with Stratus Low-Power Optimization methods
- Designing and Developing Tensilica HiFi DSP based subsystem IP for the next generation of audio SoC chips, exploring power-saving methods from architecture level, such as light-load mode
- Participating in the design process starting with high-level conceptual and architectural discussions and ending with micro-architecture specifications for the next generation of ANC (Active Noise Cancelation) IP design
- With basic understanding about audio signal processing block, such as interpolator, decimator and programmable filter etc.
- Machine learning extension for Qualcomm/CSR Kalimba DSP by supporting packed half-word and byte MAC
- Built cycle-accurate model for kalimba DSP prefetch unit
- Designed and implemented a biquad accelerator to accelerate biquad filtering operations for ANC algorithms; instantiated as a hardware block interfacing with Cadence HiFi 4 DSP and supporting extended TIE instructions.
Education
PhD - Microelectronics
University of Southampton
2014.12 - 2019.01
MSc - Microelectronic System Design
University of Southampton
2013.09 - 2014.12
BSc - Electronic Engineering
University of Changzhou
2009.09 - 2013.06
Skills
- Programming Languages: SystemVerilog, SystemC, Python, MATLAB, SPICE
- EDA tools : JasperGold (Formal), Conformal ECO, SpyGlass (CDC/Linting), Verdi, RTL-Architect, Design Compiler, Cadence, Stratus, PTPX, PowerArtist
- Architecture & IP: ARM AMBA/AXI, ARM-based SoCs, NoC, Tensilica, Low-power design, HLS
- Analysis & Research: Micro-architecture specification, PPA optimization, Cycle-accurate modeling
Certification
- Comprehensive Digital IC Implementation and Sign-Off training using Synopsys Fusion Compiler
- EUROPRACITCE
Languages
Language: English (proficient) and Mandarin (native)
PUBLICATIONS
- A Cost-Efficient Error-Resilient Approach to Distributed Arithmetic for Signal Processing Elsevier Microelectronics Reliability,2019
- An ultra-low-power variable-accuracy bit-serial FFT butterfly processing element for IoT sensors IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2016
- A Variation-aware Design Methodology for Distributed Arithmetic MDPI Electronics, 2018
Timeline
Staff SoC Design Engineer
ARM
2025.02 - Current
Staff Design Engineer
Qualcomm
2019.02 - 2024.12
PhD - Microelectronics
University of Southampton
2014.12 - 2019.01
MSc - Microelectronic System Design
University of Southampton
2013.09 - 2014.12
BSc - Electronic Engineering
University of Changzhou
2009.09 - 2013.06