Ramesh Upputuri
Milton Keynes,United Kingdom
Summary
Senior Analog/Mixed-Signal IC Designer with 8+ years of experience delivering silicon-proven solutions for Automotive, High-Speed Interfaces, and Flexible Electronics. Expert in low-power PMIC design and PLL architectures. Recently validated the industry’s first flexible PLL using TFTs (NFET-only). Skilled in post-silicon validation, Python automation, and driving first-pass silicon success.
Overview
9
9
years of professional experience
6
6
years of post-secondary education
Work history
Senior Analog Design Engineer
Pragmatic semiconductor
Cambridge
11.2024 - Current
- Flexible Electronics : Designed and validated industry’s first flexible PLL using Thin-Film Transistors (TFTs), initially targeting 100kHz for microprocessor applications.
- NFC Application: Scaled PLL design to 848kHz for NFC applications, successfully validated output clock
- Unipolar Design: Overcame severe design constraints including NFET-only availability, high process variations, and temperature variation to achieve functional chip.
Senior Analog Designer
Indie Semiconductor
Edinburgh, Scotland
12.2022 - 10.2024
- Post-Silicon Validation: Led validation for LIN and CAN drivers , developing Python scripts for automated bench testing and verifying analog functionality.
- High-Voltage Design: Designed switched-capacitor amplifier to sense VGS of FETs within high-voltage reverse battery protection IP.
- Reliability: Performed Safe Operating Area (SOA) and floating node checks to ensure robust silicon reliability ; optimized LDO current limits for updated chip versions.
- Designed high-speed strong arm latched comparator for ADCs.
Senior Member of Technical Staff
Rambus Chip Technologies
Bangalore, India
09.2020 - 11.2022
- DDR5 Interface (6.4Gbps): Spearheaded Tx redesign for next-gen DDR5 interfaces, resulting in successful silicon performance.
- Low Power: Reduced Bandgap reference quiescent current by 50% through architectural improvements, achieving first-pass silicon success.
- Signal Integrity: Executed LDO design improvements inside PLL loop and performed top-level clocking simulations to minimize jitter.
- Silicon Debug: Root-caused Electrical Overstress (EOS) degradation and implemented design fixes for superior reliability.
- Improved reset Tx design for better Ron performance.
Design Engineer
Cirel Systems Pvt. Ltd
Bangalore, India
07.2017 - 08.2020
- Area Reduction (50%): Architected a unified Low-IQ LDO (500nA) supporting a wide load range (150mA), replacing a dual-LDO topology to reduce die area by 50%.
- Sensor Interface: Designed a constant-gm rail-to-rail amplifier (Gain 1-10) for sensor applications, validated successfully in silicon.
- Power Management: Designed a 1.8V LDO for digital loads and a Power-on-Reset (POR) verified for wide rise/fall times (1µs to 1s)
Education
Master of Science - Microelectronics
IIT Bombay
Mumbai 07.2015 - 05.2017
Bachelor of Science - Electronics & Communication
NIT Calicut
Calicut 07.2010 - 05.2014
Skills
- Analog Mixed Signal IC Design
EDA Tools: Cadence Virtuoso
Design Expertise: PLL, PMIC (LDO, Bandgap reference), High-Speed Interfaces (DDR5), Sensor AFE (Amplifiers)
Accomplishments
- AIR 29 (Top 0.01%): Secured All India Rank 29 in GATE (Electronics & Communication) among ~200k applicants.
- AIR 4159 (Top 0.4%): Secured top rank in AIEEE 2010 among ~1.1 million candidates.
Timeline
Senior Analog Design Engineer
Pragmatic semiconductor
11.2024 - Current
Senior Analog Designer
Indie Semiconductor
12.2022 - 10.2024
Senior Member of Technical Staff
Rambus Chip Technologies
09.2020 - 11.2022
Design Engineer
Cirel Systems Pvt. Ltd
07.2017 - 08.2020
Master of Science - Microelectronics
IIT Bombay
07.2015 - 05.2017
Bachelor of Science - Electronics & Communication
NIT Calicut
07.2010 - 05.2014