Priyanka Shukla
Bangalore,India
Summary
Experienced engineer with focus on leading complex projects and driving innovation in engineering solutions. Deliver high-quality results by leveraging strong technical expertise and collaborative leadership. Excel in optimising processes and fostering team development to achieve project goals.
Overview
13
13
years of professional experience
2
2
years of post-secondary education
Work History
Principal engineer
ARM Embedded Technologies
Bengaluru, India
10.2022 - Current
- Led the droplet CPU/GPU teams to deliver on-schedule executions of medium cores.
- Led design process for improved system efficiency and DVFS targets.
- Was responsible for delivering droplets to customers.
- Responsible for delivering N3P and N3E tech nodes GDS2 to the customer with full quality metrics.
- Worked on ECO cycles, power roll-up, EMIR, LEC, and CLP sign-off checks as well.
- Worked on many different methodologies, including stylus for physical implementation, achieving PPA.
- Assisted in strategic planning of engineering projects to meet company objectives.
- Initiated regular training sessions improving team's technical skills.
- Collaborated with stakeholder groups for efficient project execution.
- Developed new technical solutions, resulting in increased productivity.
Technical Lead
Qualcomm India - BDC Compute
Bengaluru, India
06.2021 - 10.2022
- Worked on Turing/VAPSS FE execution for various tape-outs.
- Responsible for timing constraints, power intent, and functional ECO.
- Build up the setup for Fusion compiler synthesis in FE for MCMM.
- Responsible for delivering the 4nm project for Turing HM, focusing on target leakage, congestion, and timing.
SD Lead
Intel Technology India Pvt. Ltd. – C2DG Group
Bengaluru, India
01.2019 - 05.2021
- Responsible for delivering the PCIE Subsystem to the SOC team.
- Worked FC-level and block-level sign-off for PRQ dies for PCIe subsystem.
- Worked on Tape-in checklists and quality delivery of PCIE among many global stakeholders.
- Responsible for the closure of the partition from RTL to GDS with MV domain and complex clocking structure.
- Worked in PCIe subsystem as partition owner of complex partitions of PSF functionality, and controller.
- Helped other team members closely to understand Quality, Clock, and Design calibre issues.
- Worked with the Global Power team for PTPX runs for the subsystem, and to define the power features at the subsystem level.
SOC Design Engineer
Intel Technology India Pvt. Ltd.
Bengaluru, India
07.2012 - 12.2018
- Responsible for completing the partition from RTL to GDS.
- Worked on PSF units with MV domains, and timing criticality.
- Responsible for PNR, timing, and ECO for block closure.
Education
Bachelor of Technology - Electronics & Instrumentation
MJP Rohilkhand University
IndiaDiploma - VLSI & Emdedded designs
CDAC Noida
India Master of Technology - VLSI and Embedded designs
PESIT
Bengaluru, India 06.2011 - 07.2013
Skills
- Synthesis
- Physical Design
- Low Power
- UPF
- STA
- LEC
- EMIR
- DFT
- Timing constraints
- Floor planning
EDA TOOLS
Genus, Innovus, ICC, FC, DC, Tempus, PT, PTPX, QRC, Conformal, RHSC
Timeline
Principal engineer
ARM Embedded Technologies
10.2022 - Current
Technical Lead
Qualcomm India - BDC Compute
06.2021 - 10.2022
SD Lead
Intel Technology India Pvt. Ltd. – C2DG Group
01.2019 - 05.2021
SOC Design Engineer
Intel Technology India Pvt. Ltd.
07.2012 - 12.2018
Master of Technology - VLSI and Embedded designs
PESIT
06.2011 - 07.2013
Bachelor of Technology - Electronics & Instrumentation
MJP Rohilkhand University
Diploma - VLSI & Emdedded designs
CDAC Noida
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