Payesvini Babu

A-ACK

Ownership of Trap Testing of v9.6A

• Investigated the new trap registers and instructions
• Developed tests using internal trap methodology
• Added tests in SVE, SME, ASIMD/FP areas
• Achieved 80% coverage

Ownership of v9.5A MTE

• Investigated the new feature added in Memory Tagging Extension
• Randomized templates developed for this feature using RAVEN
• Came up with interesting data values and interesting data tests developed
• Tests also developed using self check automation tool
• 100% coverage closure achieved in 3 months

M-ACK - Ownership of v8.2M ISA

• Resumed random instruction generation tool that was last carried out by the team in 2018
• Worked with methodology team to improvise the random instruction tool generation flow which is more efficient then the previous flow.
• Developed new v8.2M Pycharm based tada! templates for interesting data
• Created a flow for v8M-ACK that carries out constraints and consistency checks for various target configuration entries

R-ACK

• Maintenance phase - Partner issue fixes, Coverage closures, Regression fixes

Detailed Investigation on v8.2M features

• Ramped-up for the new cadence for M architecture v8.2M
• Created scenarios for v8.2M in PMU, NSRO(Non-Secure Read Only), PPB(Private Peripheral Bus) and Exception Handling
• Multiple discussions with team members and Architects for scenarios' validation

Worked in three groups with bandwidth : A-ACK 50%, R-ACK 25%, M-ACK 25%

A-ACK - PGT development

• Updated CORE tests based on Annual Cadence Spec-Updates
• Existing CORE ACK suites had only 4k and 16k PageTable files. Developed and qualified ~40 PageTables(PGTs) for 64k sized-granule.
• 64k PGTs developed for multiple suites likes FP, INT, ASIMD and EXCEP

R-ACK

• Supported Internal partner for v8r64-ACK by providing fixes for issues faced in RTL.

M-ACK

• Involved in maintenance activities like coverage closure, partner support and spec-updates

Ownership of Pointer Authentication and Branch Target Identification

• Took ownership of BTI feature in PACBTI
• Developed ~40 directed tests using Embedded C and Assembly code
• Achieved 100% coverage for PACBTI

Ownership of Performance Monitoring Unit

• Re-structured all existing Performance Monitoring Unit (PMU) tests for robustness with related updates in Methodology
• Ramp-up of new feature in v8.1M called PACBTI (Pointer Authentication and Branch Target Identification Extension)

Ownership of Custom DataPath Extension

• Took ownership of newly added feature in v8.xM Custom DataPath Extension(CDE)
• Developed ~30 directed tests in v8.0M and v8.1M using Embedded C and Assembly code
• Achieved 100% coverage for CDE

• Aided the team for achieving EAC milestone for v8.1M architecture.
• Populated run-time and compile-time skips for all the v8.1M tests.
• Worked on bins that have been missing over the years in coverage of v8.0M and closed by updating/adding new stimulus.
• Developed tests for Undefined opcodes.
• Debugged all v8.1M tests failing in newly developed pseudocode model.

Ownership of Data Independent Timing

• Took ownership of a newly added feature in v8.1M called Data Independent Timing(DIT)
• Came up with a specific test structure that can be re-used in multiple DIT tests .
• Developed ~20 directed tests using embedded C and assembly code.
• Meticulously worked and achieved 100% coverage in EAC quality

• Ramped up on v8M ARM architecture and ISA compliance.
• For ISA compliance, generated executable binary from a random generation tool based on a controlled input stimulus.
• Debugged templates generated from RAVEN wrt to Spec-Updates

IR aware STA.

• Cadence® tools such as VoltusTM, TempusTM and Synopsys® tools such as HSPICETM was employed to perform the analysis.
• Dynamic analysis for ARM®CortexTMA55 in 7nm technology was carried out using Voltus and the drop was fixed to reasonable limits. Spice simulation of certain cells using HSPICE was carried out to get the scaling values to characterize the .libs.
• After characterization of libraries(trilibs),the .iv(instance-voltage) file from Voltus is back-annotated and STA was run in Tempus.
• The traditional flat-derating approach was compared with IR aware STA/trilib approach. Timing from SPICE can be used as the golden reference to compare the two approaches.