PADMINI PRAKASH

Design-for-Test professional with 9+ years of work experience on technologies from 40-16nm of ASIC/SOC's. Worked on all aspects of DFT design implementation and verification on a few thousand to multi-billion transistor designs

• Published multiple papers in IEEE
• MS in Electrical Engineering from University of Southern California,USA, with GPA of 3.7
• Involved in bring up and debug support on ATE bring up for multiple projects on MBIST, ATPG, DDR, PCIE and other mixed signal blocks
• Worked on innovative ideas for enabling DFT MBIST and Scan testing on Emulation platform, DFT LINT checks and DFT related connectivity checks in a few weeks to enable quick testing of chips
• Collaborated with cross departmental groups to gather requirements for DFT pattern generation and delivery for testing on Silicon
• Mentored 4 interns on different tools and concepts in DFT to fully equip them to understand and work on DFT
• Hands on experience in pre-silicon verification on co-processor using UVM/VMM methodology
• Pre silicon validation and debugging of USB 2.0 and 3.0 interface and system bring up for various projects on FPGA (Virtex 6/dual SXP) and Virtual platform, Paper on “Accelerating GLS simulation closure n DFT with Emulator hardware” selected for presentation in International Test Conference (ITC India 2021)
• Published a paper on “Automatic MBIST Scheduling Engine” in DTTC, 2019 and presented in IEEE CONECCT

• Won Spot Recognition Award 2018 for excellent individual contribution in projects. Won Infosys Global Team Excellence Team Award, 2017.