Anjana Krishnakumar

Analog Design and Layout

• Designed an opamp as part of initial training program with the given specifications for output swing, supply voltage, ICMR, slew rate etc.
• Captured schematics in Cadence Virtuoso and performed LVS checks on top-level sensor die design

Behavioral Modelling for Verification

• Developed a self-checking System Verilog testbench to validate the combinational logic of an analog-digital converter module.
• Implemented functional checks to compare DUT output against calculated expected results, with automated error detection and reporting.
• Achieved high coverage and confidence in functional correctness of mixed-signal interface logic.

SystemVerilog Mixed-Signal Sensor Array Simulation

• Developed a System Verilog testbench to simulate a large-scale analog pixel sensor array using real-number modeling (wreal4state), including realistic readout timing and analog behavior.
• Generated grayscale image outputs (.ppm) from simulation results, enabling visual validation of sensor behavior.