Ahmed Rahim

Although based in the UK, I'm a key member of the unit level verification team (based in Boston, MA, USA) responsible for verifying the Load/Store Unit and L1 Data Cache (LSDC) of the next generation AMD Zen CPU core.

Key Responsibilities:

• Day-to-day maintenance of unit-level (SystemVerilog/UVM and C++ based) LSDC and TLB testbench.
• Analyzing coverage runs, identifying stimulus holes and enhancing the existing stimulus.
• Debugging failures from nightly regression.
• Creating testplans and developing new checkers/stimulus for new u-arch features.
• Developing new (and maintaining existing) power regression tests (using a modified version of the unit-level stimulus) for the new Early Power Analysis flow.

Miscellaneous:

• Liaising with the team in Austin (TX, USA) to gain expertise on the TLB verification infrastructure and gradually transitioning into a local expert for the CPU cores team in the UK.
• Participating in cross-site effort to port existing (SystemVerilog/UVM based) components to the proprietary C++ based verification framework.
• Conducting interviews for graduate and internship roles in the CPU cores team in the UK.